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1 ? fn7311.8 EL5172, el5372 250mhz differential line receivers the EL5172 and el5372 are single and triple high bandwidth amplifiers designed to extract the difference signal from noisy environments. they are primarily targeted for applications such as receiving signals from twisted-pair lines or any application where common mode noise injection is likely to occur. the EL5172 and el5372 are stable for a gain of one and requires two external resistors to set the voltage gain. the output common mode level is set by the reference pin (v ref ), which has a -3db band width of over 120mhz. generally, this pin is grounded but it can be tied to any voltage reference. the output can deliver a maximum of 60ma and is short circuit protected to withstand a temporary overload condition. the EL5172 is available in the 8 ld soic and 8 ld msop packages and the el5372 in a 24 ld qsop package. both are specified for operation over the full -40c to +85c temperature range. features ? differential input range 2.3v ? 250mhz 3db bandwidth ? 800v/s slew rate ? 60ma maximum output current ? single 5v or dual 5v supplies ? low power - 5ma to 6ma per channel ? pb-free available (rohs compliant) applications ? twisted-pair receivers ? differential line receivers ? vga over twisted-pair ? adsl/hdsl receivers ? differential to single-ended amplification ? reception of analog signals in a noisy environment pinouts EL5172 (8 ld soic, msop) top view el5372 (24 ld qsop) top view 1 2 3 4 8 7 6 5 out vs- vs+ en fb in+ in- ref - + 1 2 3 4 16 15 14 13 5 6 7 12 11 9 8 10 20 19 18 17 24 23 22 21 ref1 inp1 inn1 nc ref2 inp2 inn2 nc ref3 inp3 inn3 nc nc fb1 out1 nc vsp vsn nc fb2 out2 en fb3 out3 - + - + - + data sheet january 25, 2008 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2002-2005, 2008. all rights reserved. all other trademarks mentioned are the property of their respective owners .
2 fn7311.8 january 25, 2008 ordering information part number part marking package pkg. dwg. # EL5172is 5172is 8 ld soic (150 mil) mdp0027 EL5172is-t7* 5172is 8 ld soic (150 mil) mdp0027 EL5172is-t13* 5172is 8 ld soic (150 mil) mdp0027 EL5172isz (note) 5172isz 8 ld soic (150 mil) (pb-free) mdp0027 EL5172isz-t7* (note) 5172isz 8 ld soic (150 mil) (pb-free) mdp0027 EL5172isz-t13* (note) 5172isz 8 ld soic (150 mil) (pb-free) mdp0027 EL5172iy h 8 ld msop (3.0mm) mdp0043 EL5172iy-t7* h 8 ld msop (3.0mm) mdp0043 EL5172iy-t13* h 8 ld msop (3.0mm) mdp0043 EL5172iyz (note) baawa 8 ld msop (3.0mm) (pb-free) mdp0043 EL5172iyz-t7* (note) baawa 8 ld msop (3.0mm) (pb-free) mdp0043 EL5172iyz-t13* (note) baawa 8 ld msop (3.0mm) (pb-free) mdp0043 el5372iu el5372iu 24 ld qsop (150 mil) mdp0040 el5372iu-t7* el5372iu 24 ld qsop (150 mil) mdp0040 el5372iu-t13* el5372iu 24 ld qsop (150 mil) mdp0040 el5372iuz (note) el5372iuz 24 ld qsop (150 mil) (pb-free) mdp0040 el5372iuz-t7* (note) el5372iuz 24 ld qsop (150 mil) (pb-free) mdp0040 el5372iuz-t13* (note) el5372iuz 24 ld qsop (150 mil) (pb-free) mdp0040 *please refer to tb347 for detai ls on reel specifications. note: these intersil pb-free plastic packaged products employ special pb-free material sets; molding compounds/die attach materi als and 100% matte tin plate plus anneal - e3 terminatio n finish, which is rohs compliant and compat ible with both snpb and pb-free solderin g operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements o f ipc/jedec j std-020. EL5172, el5372
3 fn7311.8 january 25, 2008 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute maxi mum ratings (t a = +25c) thermal information supply voltage (v s + to v s -) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12v maximum output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60ma storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c operating junction temperature . . . . . . . . . . . . . . . . . . . . . . +135c ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. electrical specifications v s + = +5v, v s - = -5v, t a = +25c, v in = 0v, r l = 500 , r f = 0, r g = open, c l = 2.7pf, unless otherwise specified. parameter description conditions min typ max unit ac performance bw -3db bandwidth a v =1, c l = 2.7pf 250 mhz a v =2, r f = 1000 , c l = 2.7pf 70 mhz a v =10, r f = 1000 , c l = 2.7pf 10 mhz bw 0.1db bandwidth a v =1, c l = 2.7pf 25 mhz sr slew rate v out = 3v p-p , 20% to 80%, EL5172 550 800 1000 v/s v out = 3v p-p , 20% to 80%, el5372 550 700 1000 v/s t stl settling time to 0.1% v out = 2v p-p 10 ns t ovr output overdrive recovery time 20 ns gbwp gain bandwidth product 100 mhz v ref bw (-3db) v ref -3db bandwidth a v =1, c l = 2.7pf 120 mhz v ref sr v ref slew rate v out = 2v p-p , 20% to 80% 600 v/s v n input voltage noise at f = 11khz 26 nv/ hz i n input current noise at f = 11khz 2 pa/ hz hd2 second harmonic distortion v out = 1v p-p , 5mhz -66 dbc v out = 2v p-p , 50mhz -63 dbc hd3 third harmonic distortion v out = 1v p-p , 5mhz -84 dbc v out = 2v p-p , 50mhz -76 dbc dg differential gain at 3.58mhz r l = 150 , a v = 2 0.04 % d differential phase at 3.58mhz r l = 150 , a v = 2 0.41 e s channel separation at 100khz el5372 only 90 db input characteristics v os input referred offset voltage 7 25 mv i in input bias current (v in , v inb , v ref )-14-6-3a r in differential input resistance 300 k c in differential input capacitance 1pf dmir differential input range 2.1 2.38 2.5 v cmir+ common mode positive input range at v in +, v in -3.33.5v cmir- common mode positive input range at v in +, v in - -4.5 -4.3 v refin+ reference input positive voltage range v in + = v in - = 0v 3.3 3.7 v v refin- reference input negative voltage range v in + = v in - = 0v -3.9 -3.6 EL5172, el5372
4 fn7311.8 january 25, 2008 cmrr input common mode rejection ratio v in = 2.5v 75 95 db gain gain accuracy v in = 1 0.985 1 1.015 v output characteristics v out positive output voltage swing r l = 500 to gnd 3.3 3.63 v negative output voltage swing r l = 500 to gnd -3.87 -3.5 v i out (max) maximum output current r l = 10 60 95 ma r out output impedance 100 m supply v supply supply operating range v s + to v s -4.7511v i s (on) power supply current per channel - enabled 4.6 5.6 7 ma i s (off) + positive power supply current - disabled en pin tied to 4.8v, EL5172 80 100 a en pin tied to 4.8v, el5372 1.7 5 a i s (off) - negative power supply current - disabled -150 -120 -90 a psrr power supply rejection ratio v s from 4.5v to 5.5v 50 58 db enable t en enable time 150 ns t ds disable time 1.4 s v ih en pin voltage for power-up v s + - 1.5 v v il en pin voltage for shut-down v s + - 0.5 v i ih-en en pin input current high per channel at v en = 5v 40 60 a i il-en en pin input current low per channel at v en = 0v -10 -3 a electrical specifications v s + = +5v, v s - = -5v, t a = +25c, v in = 0v, r l = 500 , r f = 0, r g = open, c l = 2.7pf, unless otherwise specified. (continued) parameter description conditions min typ max unit EL5172, el5372
5 fn7311.8 january 25, 2008 pin descriptions EL5172 el5372 pin name pin function 1 fb feedback input 2 in+ non-inverting input 3 in- inverting input 4 ref sets the common mode output voltage level 5en enabled when this pin is floating or the applied voltage v s + - 1.5 6 vs+ positive supply voltage 7 vs- negative supply voltage 8 out output voltage 1, 5, 9 ref1, 2, 3 reference input, controls common-mode output voltage 2, 6, 10 inp1, 2, 3 non-inverting inputs 3, 7, 11 inn1, 2, 3 inverting inputs 4, 8, 12, 18, 21, 24 nc no connect; grounded for best crosstalk performance 13, 16, 22 out1, 2, 3 non-inverting outputs 14, 17, 23 fb1, 2, 3 feedback from outputs 15 en enabled when this pin is floating or the applied voltage v s + - 1.5 19 vsn negative supply 20 vsp positive supply EL5172, el5372
6 fn7311.8 january 25, 2008 connection diagrams 1 2 3 4 16 15 14 13 5 6 7 12 11 9 8 10 20 19 18 17 24 23 22 21 ref1 inp1 inn1 nc ref2 inp2 inn2 nc ref3 inp3 inn3 nc nc fb1 out1 nc vsp vsn nc fb2 out2 en fb3 out3 r sr3 50 r sn3 50 r sp3 50 r sr2 50 r sn2 50 r sp2 50 r sr1 50 r sn1 50 r sp1 50 ref1 inp1 inn1 ref2 inp2 inn2 ref3 inp3 inn3 +5v c l2 2.7pf c l3 2.7pf out3 out1 r g r f r l1 500 c l1 2.7pf -5v out2 r g r f r l2 500 enable r l3 500 r g r f fb inp inn ref out vsn vsp en 1 2 3 4 8 7 6 5 inp inn ref r g r s3 en vout -5v +5v r f = 0 50 r s2 50 r s2 50 c l 2.7pf r l 500 EL5172 el5372 EL5172, el5372
7 fn7311.8 january 25, 2008 typical performance curves figure 1. frequency response vs supply voltage f igure 2. frequency response vs supply voltage figure 3. frequency response vs various gain figure 4. frequency response vs c l figure 5. frequency response vs c l figure 6. frequency response for various r f 4 3 1 0 -2 -3 -5 -6 10m 100m 1g magnitude (db) frequency (hz) -4 -1 2 1m v s = 5v v s = 2.5v a v = 1, r l = 500 , c l = 2.7pf 4 3 1 0 -2 -3 -5 -6 10m 100m 1g frequency (hz) -4 -1 2 1m v s = 5v v s = 2.5v magnitude (db) a v = 1, r l = 100 , c l = 2.7pf 4 3 1 0 -2 -3 -5 -6 10m 100m 1g normalized gain (db) frequency (hz) -4 -1 2 1m a v = 1 a v = 2 a v = 5 a v = 10 v s = 5v, r l = 500 , c l = 2.7pf 5 4 2 1 -1 -2 -4 -5 10m 100m 1g frequency (hz) -3 0 3 1m magnitude (db) v s = 5v, a v = 1, r l = 500 c l = 56pf c l = 33pf c l = 15pf c l = 10pf c l = 2.7pf 10m 100m 1g frequency (hz) 1m magnitude (db) 5 4 2 1 -1 -2 -4 -5 -3 0 3 v s = 5v, a v = 1, r l = 500 c l = 2.7pf c l = 10pf c l = 15pf c l = 33pf c l = 56pf 4 3 1 0 -2 -3 -5 -6 10m 100m 1g normalized gain (db) frequency (hz) -4 -1 2 1m r f = 200 r f = 500 v s = 5v, a v = 2, r l = 500 , c l = 2.7pf r f = 1k EL5172, el5372
8 fn7311.8 january 25, 2008 figure 7. frequency response for v ref figure 8. open loop gain figure 9. output impedance vs frequency figure 10. psrr vs frequency figure 11. cmrr vs frequency figure 12. voltage and current noise vs frequency typical performance curves (continued) 4 3 1 0 -2 -3 -5 -6 10m 100m 1g norminalized gain (db) frequency (hz) -4 -1 2 1m v s = 2.5v v s = 5v a v = 1, r l = 500 , c l = 2.7pf 60 50 30 20 0 -10 -30 -40 100k 10m 500m gain (db) frequency (hz) -20 10 40 10k 1m 100m 270 225 135 90 0 -45 -135 -180 -90 45 180 phase () 100 10 1 0.1 100k 1m 100m impedence ( ) frequency (hz) 10k 10m 0 -10 -30 -50 -60 -80 -90 10k 1m 100m psrr (db) frequency (hz) -70 -40 -20 1k 100k 10m psrr+ psrr- 1m 100m cmrr (db) frequency (hz) 100k 10m 1g 100 90 70 60 40 30 10 0 20 50 80 1k 100 10 1 voltage noise (nv/ hz) 100 100k 10m frequency (hz) 10 10k 1m 1k e n i n current noise (pa/ hz) EL5172, el5372
9 fn7311.8 january 25, 2008 figure 13. channel isolation vs frequency figure 14. harmonic distortion vs output voltage figure 15. harmonic distortion vs load resistance figure 16. harmonic distortion vs frequency figure 17. small signal transient response f igure 18. large signal transient response typical performance curves (continued) 1m 100m gain (db) frequency (hz) 100k 10m 1g 0 -10 -30 -40 -60 -70 -90 -100 -80 -50 -20 ch1 <=> ch2, ch2 <=> ch3 ch1 <=> ch3 -45 -50 -60 -70 -80 -85 distortion (db) -75 -65 -55 25 v op-p (v) 1 4 6 3 7 h d 2 ( a v = 2 ) h d 3 ( a v = 2 ) hd 2 ( a v = 1 ) hd3 (a v = 1) v s = 5v, r l = 500 , f = 5mhz -45 -50 -60 -70 -80 -85 distortion (db) -75 -65 -55 200 700 r load ( ) 100 600 900 400 1000 hd3 (a v = 1) -80 300 500 800 h d 3 ( a v = 2 ) v s = 5v, f = 5mhz, v op-p = 1v @a v = 1, v op-p = 2v @a v = 2 h d 2 ( a v = 2 ) h d 2 ( a v = 1 ) -40 -50 -60 -70 -90 distortion (db) -80 525 frequency (mhz) 035 15 40 -100 10 20 30 h d 2 ( a v = 2 ) hd3 (a v = 1) h d 2 ( a v = 1 ) v s = 5v, r l = 500 , v op-p = 1v for a v = 1, v op-p = 2v for a v = 2 h d 3 ( a v = 2 ) 50mv/div 10ns/div 0.5v/div 10ns/div EL5172, el5372
10 fn7311.8 january 25, 2008 simplified schematic figure 19. enabled response f igure 20. disabled response figure 21. package power dissipation vs ambient temperature figure 22. package power dissipation vs ambient temperature typical performance curves (continued) ch1 ch2 100ns/div m = 100ns, ch1 = 200mv/div, ch2 = 5v/div ch1 ch2 400ns/div m = 400ns, ch1 = 200mv/div, ch2 = 5v/div 486mw ja = +206c/w msop8 870mw ja = +115c/w qsop24 1.2 1.0 0.8 0.6 0.4 0 0 255075100 150 ambient temperature (c) power dissipation (w) 125 85 jedec jesd51-3 low effective thermal conductivity test board 0.2 625mw ja = +160c/w soic8 1.136w ja = +88c/w qsop24 1.4 1.2 1.0 0.8 0.6 0.2 0 0 255075100 150 ambient temperature (c) power dissipation (w) 125 85 jedec jesd51-7 high effective thermal conductivity test board 0.4 909mw ja = +110c/w soic8 870mw ja = +115c/w msop8/10 r 2 r 1 r 4 r 3 r d2 r d1 q 8 fbn q 4 fbp q 3 vin- q 2 vin+ q 1 q 6 v s + i 4 i 3 i 2 i 1 q 7 v b1 v s - 25 q 9 v b2 x1 v out c c EL5172, el5372
11 fn7311.8 january 25, 2008 description of operat ion and application information product description the EL5172 and el5372 are wide bandwidth, low power and single/differential ended to single ended output amplifiers. the EL5172 is a single channel differential to single ended amplifier. the el5372 is a triple channel differential to single ended amplifier. the EL5172 and el5372 are internally compensated for closed loop gain of +1 or greater. connected in gain of 1 and driving a 500 load, the EL5172 and el5372 have a -3db bandwidth of 250mhz. driving a 150 load at gain of 2, the bandwidth is about 50mhz. the bandwidth at the ref input is about 450mhz. the EL5172 and el5372 are available with a power-down feature to reduce th e power while the amplifier is disabled. input, output and supply voltage range the EL5172 and el5372 have been designed to operate with a single supply voltage of 5v to 10v or a split supplies with its total voltage from 5v to 10v. the amplifiers have an input common mode voltage range from -4.3v to 3.3v for 5v supply. the differential mode input range (dmir) between the two inputs is about from -2.3v to +2.3v. the input voltage range at the ref pin is from -3.6v to 3.3v. if the input common mode or differential mode signal is outside the above-specified ranges, it will cause the output signal to be distorted. the output of the EL5172 and el5372 can swing from -3.8v to 3.6v at 500 load at 5v supply. as the load resistance becomes lower, the output swing is reduced respectively. over all gain settings the gain setting for the EL5172 and the el5372 is similar to the conventional operational am plifier. the output voltage is equal to the difference of the inputs plus v ref and then times the gain. figure 23. choice of feedback resistor and gain bandwidth product for applications that require a gain of +1, no feedback resistor is required. just short the out pin to the fb pin. for gains greater than +1, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. as this pole becomes smaller, the amplifier's phase margin is reduced. this causes ringing in the time domain and peaking in the frequency domain. therefore, r f has some maximum value that should not be exceeded for optimum performance. if a large value of r f must be used, a small capacitor in the few pico farad range in parallel with r f can help to reduce the ringing and peaking at the expense of reducing the bandwidth. the bandwidth of the EL5172 and el5372 depends on the load and the feedback network. r f and r g appear in parallel with the load for gains other than +1. as this combination gets smaller, the bandwidth falls off. consequently, r f also has a minimum value that should not be exceeded for optimum bandwidth performance. for a gain of +1, r f = 0 is optimum. for the gains other than +1, optimum response is obtained with r f between 500 to 1k . for a v = 2 and r f = r g = 1k , the bw is about 80mhz and the frequency response is very flat. the EL5172 and el5372 have a gain bandwidth product of 100mhz. for gains 5, its bandwidth can be predicted by equation 1: driving capacitive loads and cables the EL5172 and el5372 can drive 56pf capacitance in parallel with 500 load to ground with 4db of peaking at gain of +1. if less peaking is desired in applications, a small series resistor (u sually between 5 to 50 ) can be placed in series with each output to eliminate most peaking. however, this will reduce the gain slightly. if the gain setting is greater than 1, the gain resistor r g can then be chosen to make up for any gain loss which may be created by the additional series resistor at the output. when used as a cable driver, double termination is always recommended for reflection-free performance. for those applications, a back-termination series resistor at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. however, other applications may have high capacitive loads without a back-termination resistor. again, a small series resistor at the output can help to reduce peaking. disable/power-down the EL5172 and el5372 can be disabled and its outputs placed in a high impedance state. the turn-off time is about 1.4s and the turn-on time is about 150ns. when disabled, the amplifier's supply current is reduced to 80a for i s + and v o v ( in +v in -v ref + ) 1 r f r g -------- + ?? ?? ?? ? = - + - + g/b v o en v in + v in - v ref fb r g r f gain bw 100mhz = (eq. 1) EL5172, el5372
12 fn7311.8 january 25, 2008 120a for i s - typically, thereby effe ctively eliminating the power consumption. the amplifier's power-down can be controlled by standard cmos signal levels at the enable pin. the applied logic signal is relative to v s + pin. letting the en pin float or applying a signal that is less than 1.5v below v s + will enable the amplifier. the amplifier will be disabled when the signal at en pin is above v s + - 0.5v. if a ttl signal is used to control the enabled/disabled function, figure 24 could be used to convert the ttl signal to cmos signal. figure 24. output drive capability the EL5172 and el5372 have internal short circuit protection. its typical short circ uit current is 95ma. if the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. maximum reliability is maintained if the output current never exceeds 60ma. this limit is set by the design of the internal metal interconnections. power dissipation with the high output drive capability of the EL5172 and el5372, it is possible to exceed the +135c absolute maximum junction temperature under certain load current conditions. therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. the maximum power dissipation allowed in a package is determined according to equation 2: ?t jmax = maximum junction temperature ?t amax = maximum ambi ent temperature ? ja = thermal resistance of the package assuming the ref pin is tied to gnd for v s = 5v application, the maximum power dissipation actually produced by an ic is the total quiescent supply current times the total power supply voltage, plus the power in the ic due to the load, or: for sourcing, use equation 3: for sinking, use equation 4: where: ?v s = total supply voltage ?i smax = maximum quiescent supply current per channel ?v out = maximum output voltage of the application ?r load = load resistance ?i load = load current ? i = number of channels by setting the two pd max equations equal to each other, we can solve the output current and r load to avoid the device overheat. power supply bypassing and printed circuit board layout as with any high frequency device, a good printed circuit board layout is necessary for optimum performance. lead lengths should be as short as possible. the power supply pin must be well bypassed to reduce the risk of oscillation. for normal single supply operation, where the v s - pin is connected to the ground plane, a single 4.7f tantalum capacitor in parallel with a 0. 1f ceramic capacitor from v s + to gnd will suffice. this same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. in this case, the v s - pin becomes the negative supply rail. for good ac performance, parasitic capacitance should be kept to a minimum. use of wire wound resistors should be avoided because of their additional series inductance. use of sockets should also be avoided if possible. sockets add parasitic inductance and capacitance that can result in compromised performance. minimizing parasitic capacitance at the amplifier's inverting in put pin is very important. the feedback resistor should be placed very close to the inverting input pin. strip line design techniques are recommended for the signal traces. 1k 10k 5v en cmos/ttl pd max t jmax t amax ? ja -------------------------------------------- - = (eq. 2) pd max v s i smax v s + ( v out ) v out r load ------------------- - i ? + = (eq. 3) pd max v s i smax v out ( v s - ) i load ] i ? + [ = (eq. 4) EL5172, el5372
13 fn7311.8 january 25, 2008 typical applications figure 25. twisted pair cable receiver as the signal is transmitted through a cable, the high frequency signal will be attenuated. one way to compensate for this loss is to boost the high frequency gain at the receiver side. figure 26. compensated line receiver level shifter and signal summer the EL5172 and el5372 contains two pairs of differential pair input stages, which make sure that the inputs are all high impedance inputs. to take advantage of the two high impedance inputs, the EL5172 and el5372 can be used as a signal summer to add two signals together. one signal can be applied to vin+, the second signal can be applied to ref and v in - is ground. the output is equal to equation 5: also, the EL5172 and el5372 can be used as a level shifter by applying a level control signal to the ref input. 0 v fb v inb v ref EL5172, el5372 el5173, el5373 or EL5172, el5372 v out 50 50 z o = 100 v in 50 50 r 2 v fb v inb v ref EL5172, el5372 v out v in 50 50 r 1 r 3 c 1 z o = 100 f a f c f gain (db) 1 + r 2 /r 1 1 + r 2 /(r 1 + r 3 ) v o v in ( +v ref ) gain + = (eq. 5) EL5172, el5372
14 fn7311.8 january 25, 2008 EL5172, el5372 small outline package family (so) gauge plane a2 a1 l l1 detail x 4?e seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45? a see detail ??? c 0.010 mdp0027 small outline package family (so) symbol inches tolerance notes so-8 so-14 so16 (0.150?) so16 (0.300?) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. m 2/07 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994
15 fn7311.8 january 25, 2008 EL5172, el5372 quarter size outline plast ic packages family (qsop) 0.010 c a b seating plane detail x e e1 1 (n/2) (n/2)+1 n pin #1 i.d. mark b 0.004 c c a see detail "x" a2 4?e gauge plane 0.010 l a1 d b h c e a 0.007 c a b l1 mdp0040 quarter size outline plastic packages family symbol inches tolerance notes qsop16 qsop24 qsop28 a 0.068 0.068 0.068 max. - a1 0.006 0.006 0.006 0.002 - a2 0.056 0.056 0.056 0.004 - b 0.010 0.010 0.010 0.002 - c 0.008 0.008 0.008 0.001 - d 0.193 0.341 0.390 0.004 1, 3 e 0.236 0.236 0.236 0.008 - e1 0.154 0.154 0.154 0.004 2, 3 e 0.025 0.025 0.025 basic - l 0.025 0.025 0.025 0.009 - l1 0.041 0.041 0.041 basic - n 16 24 28 reference - rev. f 2/07 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m-1994.
16 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7311.8 january 25, 2008 EL5172, el5372 mini so package family (msop) 1 (n/2) (n/2)+1 n plane seating n leads 0.10 c pin #1 i.d. e1 e b detail x 3?e gauge plane see detail "x" c a 0.25 a2 a1 l 0.25 c a b d a m b e c 0.08 c a b m h l1 mdp0043 mini so package family symbol millimeters tolerance notes msop8 msop10 a1.101.10 max. - a1 0.10 0.10 0.05 - a2 0.86 0.86 0.09 - b 0.33 0.23 +0.07/-0.08 - c0.180.18 0.05 - d 3.00 3.00 0.10 1, 3 e4.904.90 0.15 - e1 3.00 3.00 0.10 2, 3 e0.650.50 basic - l0.550.55 0.15 - l1 0.95 0.95 basic - n 8 10 reference - rev. d 2/07 notes: 1. plastic or metal protrusions of 0.15mm maximum per side are not included. 2. plastic interlead protrusions of 0.25mm maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m-1994.

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